VHDL源程序~【落照吧】

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VHDL源程序~

存着先，备份以免悲剧。。
CNT10的VHDL源程序：
--CNT10.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
ENA:IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO:OUT STD_LOGIC);
END ENTITY CNT10;
ARCHITECTURE ART OF CNT10 IS
SIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,CLR,ENA)IS
BEGIN
IF CLR='1'THEN CQI<="0000";
ELSIF CLK'EVENT AND CLK='1'THEN
IF ENA='1'THEN
IF CQI="1001"THEN
CQI<="0000";
ELSE
CQI<=CQI+'1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,CQI)IS
BEGIN
IF CLK'EVENT AND CLK='1'THEN
IF CQI<"1001"THEN
CO<='0';
ELSE
CO<='1';
END IF;
END IF;
END PROCESS;
CQ<=CQI;
END ARCHITECTURE ART;

送TA礼物

1楼2012-03-16 20:20回复

CNT9999的VHDL源程序：
--CNT9999.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CNT9999 IS
PORT(CLR:IN STD_LOGIC;
CLK:IN STD_LOGIC;
ENA:IN STD_LOGIC;
DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END ENTITY CNT9999;
CHITECTURE ART OF CNT9999 IS
COMPONENT CNT10 IS
PORT(CLK,CLR,ENA:IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO:OUT STD_LOGIC);
END COMPONENT CNT10;
SIGNAL S0,S1,S2,S3:STD_LOGIC;
BEGIN
U0:CNT10 PORT MAP(CLK,CLR,ENA,DOUT(3 DOWNTO 0),S0);
U1:CNT10 PORT MAP(S0,CLR,ENA,DOUT(7 DOWNTO 4),S1);
U2:CNT10 PORT MAP(S1,CLR,ENA,DOUT(11 DOWNTO 8),S2);
U3:CNT10 PORT MAP(S2,CLR,ENA,DOUT(15 DOWNTO 12),S3);
END ARCHITECTURE ART;

2楼2012-03-16 20:21