哪位大神看看我这个是啥意思哇。。。程序没问题都是照书上抄的

我是做智能音乐演奏器的 FPGA开发板也买完了，现在连编译都不对 ，还怎么继续哇
--预置数和音长控制模块--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cntrol IS
PORT ( clk : IN STD_LOGIC;
q : OUT INTEGER RANGE 0 TO 16383 );
END ;
ARCHITECTURE a OF cntrol IS
TYPE mystate IS ( s0, sl, s2, s3, s4, s5, s6, s7, s8, s9,
s10, s11, s12, s13, s14, s15, s16, s17, s18, s19,
s20, s21, s22, s23, s24, s25, s26, s27, s28, s29,
s30, s31, s32, s33, s34, s35, s36, s37, s38, s39,
s40, s41, s42, s43, s44, s45, s46, s47, s48, s49,
s50, s51, s52, s53, s54, s55, s56, s57, s58, s59,
s60, s61, s62, s63, s64, s65, s66, s67, s68, s69,
s70, s71, s72, s73, s74, s75, s76, s77, s78, s79,
s80, s81, s82, s83, s84, s85, s86, s87, s88, s89,
s90, s91, s92, s93, s94, s95, s96, s97, s98, s99,
s100, s101, s102, s103, s104, s105, s106, s107, s108, s109,
s110, s111, s112, s113, s114, s115, s116, s117, s118, s119,
s120, s121, s122, s123, s124,s125);
SIGNAL state : mystate;
BEGIN
PROCESS ( clk )
BEGIN
IF (clk'EVENT AND clk='1')THEN
CASE state IS
WHEN s0=>q<=12566;state<=sl;--mid 5
WHEN sl=>q<=12566;state<=s2;--mid 5
WHEN s2=>q<=12566;state<=s3;--mid 5
WHEN s3=>q<=12566;state<=s4;--mid 5
WHEN s4=>q<=11858;state<=s5;--mid 3
WHEN s5=>q<=11858;state<=s6;--mid 3
WHEN s6=>q<=12566;state<=s7;--mid 5
WHEN s7=>q<=12566;state<=s8;--mid 5
WHEN s8=>q<=13553;state<=s9;--hig 1
WHEN s9=>q<=13553;state<=s10;--hig 1
WHEN s10=>q<=13553;state<=s11;--hig 1
WHEN s11=>q<=13553;state<=s12;--hig 1
WHEN s12=>q<=13553;state<=s13;--hig 1
WHEN s13=>q<=13553;state<=s14;--hig 1
WHEN s14=>q<=13553;state<=s15;--hig 1
WHEN s15=>q<=13553;state<=s16;--hig 1
WHEN s16=>q<=12974;state<=s17;--mid 6
WHEN s17=>q<=12974;state<=s18;--mid 6
WHEN s18=>q<=12974;state<=s19;--mid 6
WHEN s19=>q<=12974;state<=s20;--mid 6
WHEN s20=>q<=13553;state<=s21;--hi9 1
WHEN s21=>q<=13553;state<=s22;--hig 1
WHEN s22=>q<=13553;state<=s23;--hig 1
WHEN s23=>q<=13553;state<=s24;--hig 1
WHEN s24=>q<=12566;state<=s25;--mid 5
WHEN s25=>q<=12566;state<=s26;--mid 5
WHEN s26=>q<=12566;state<=s27;--mid 5
WHEN s27=>q<=12566;state<=s28;--mid 5
WHEN s28=>q<=12566;state<=s29;--mid 5
WHEN s29=>q<=12566;state<=s30;--mid 5
WHEN s30=>q<=12566;state<=s31;--mid 5
WHEN s31=>q<=12566;state<=s32;--mid 5
WHEN s32=>q<=12566;state<=s33;--mid 5
WHEN s33=>q<=12566;state<=s34;--mid 5
WHEN s34=>q<=12566;state<=s35;--mid 5
WHEN s35=>q<=12566;state<=s36;--mid 5
WHEN s36=>q<=10723;state<=s37;--mid 1
WHEN s37=>q<=10723;state<=s38;--mid 1
WHEN s38=>q<=11324;state<=s39;--mid 2
WHEN s39=>q<=11324;state<=s40;--mid 2
WHEN s40=>q<=11858;state<=s41;--mid 3
WHEN s41=>q<=11858;state<=s42;--mid 3
WHEN s42=>q<=11858;state<=s43;--mid 3
WHEN s43=>q<=11858;state<=s44;--mid 3
WHEN s44=>q<=11324;state<=s45;--mid 2
WHEN s45=>q<=11324;state<=s46;--mid 2
WHEN s46=>q<=10723;state<=s47;--mid 1
WHEN s47=>q<=10723;state<=s48;--mid 1
WHEN s48=>q<=11324;state<=s49;--mid 2
WHEN s49=>q<=11324;state<=s50;--mid2
WHEN s50=>q<=11324;state<=s51;--mid2
WHEN s51=>q<=11324;state<=s52;--mid2
WHEN s52=>q<=11324;state<=s53;--mid2
WHEN s53=>q<=11324;state<=s54;--mid2
WHEN s54=>q<=16383;state<=s55; --O
WHEN s55=>q<=16383;state<=s56; --O
WHEN s56=>q<=16383;state<=s57; --O
WHEN s57=>q<=16383;state<=s58; --0
WHEN s58=>q<=16383;state<=s59; --0
WHEN s59=>q<=16383;state<=s60; --O
WHEN s60=>q<=16383;state<=s61; --0
WHEN s61=>q<=16383;state<=s62; --0
WHEN s62=>q<=12566;state<=s63;--mid 5
WHEN s63=>q<=12566;state<=s64;--mid 5
WHEN s64=>q<=12566;state<=s65;--mid 5
WHEN s65=>q<=12566;state<=s66;--mid 5
WHEN s66=>q<=11858;state<=s67;--mid 3
WHEN s67=>q<=11858;state<=s68;--mid 3
WHEN s68=>q<=12566;state<=s69;--mid 5
WHEN s69=>q<=12566;state<=s70;--mid 5
WHEN s70=>q<=13553;state<=s71;--hig 1
WHEN s71=>q<=13553;state<=s72;--hig 1
WHEN s72=>q<=13553;state<=s73;--hig 1
WHEN s73=>q<=13553;state<=s74;--hig 1
WHEN s74=>q<=13553;state<=s75;--hig 1
WHEN s75=>q<=13553;state<=s76;--hig 1
WHEN s76=>q<=13337;state<=s77;--mid 7
WHEN s77=>q<=13337;state<=s78;--mid 7
WHEN s78=>q<=12974;state<=s79;--mid 6
WHEN s79=>q<=12974;state<=s80;--mid 6
WHEN s80=>q<=12974;state<=s81;--mid 6
WHEN s81=>q<=12974;state<=s82;--mid 6
WHEN s82=>q<=13553;state<=s83;--hig 1
WHEN s83=>q<=13553;state<=s84;--hig 1
WHEN s84=>q<=13553;state<=s85;--hig 1
WHEN s85=>q<=13553;state<=s86;--hig 1
WHEN s86=>q<=12566;state<=s87;--mid 5
WHEN s87=>q<=12566;state<=s88;--mid 5
WHEN s88=>q<=12566;state<=s89;--mid 5
WHEN s89=>q<=12566;state<=s90;--mid 5
WHEN s90=>q<=12566;state<=s91;--mid 5
WHEN s91=>q<=12566;state<=s92;--mid 5
WHEN s92=>q<=12566;state<=s93;--mid 5
WHEN s93=>q<=12566;state<=s94;--mid 5
WHEN s94=>q<=12566;state<=s95;--mid 5
WHEN s95=>q<=12566;state<=s96;--mid 5
WHEN s96=>q<=12566;state<=s97;--mid 5
WHEN s97=>q<=12566;state<=s98;--mid 5
WHEN s98=>q<=11324;state<=s99;--mid 2
WHEN s99=>q<=11324;state<=s100;--mid 2
WHEN s100=>q<=11858;state<=s101;--mid 3
WHEN s101=>q<=11858;state<=s102;--mid 3
WHEN s102=>q<=12116;state<=s103;--mid 4
WHEN s103=>q<=12116;state<=s104;--mid 4
WHEN s104=>q<=12116;state<=s105;--mid 4
WHEN s105=>q<=12116;state<=s106;--mid 4
WHEN s106=>q<=12116;state<=s107;--mid 4
WHEN s107=>q<=12116;state<=s108;--mid 4
WHEN s108=>q<=10286;state<=s109;--low 7
WHEN s109=>q<=10286;state<=s110;--low 7
WHEN s110=>q<=10723;state<=s111;--mid 1
WHEN s111=>q<=10723;state<=s112;--mid 1
WHEN s112=>q<=10723;state<=s113;--mid 1
WHEN s113=>q<=10723;state<=s114;--mid 1
WHEN s114=>q<=10723;state<=s115;--mid 1
WHEN s115=>q<=10723;state<=s116;--mid 1
WHEN s116=>q<=10723;state<=s117;--mid 1
WHEN s117=>q<=10723;state<=s118;--mid 1
WHEN s118=>q<=16383;state<=s119; -- O
WHEN s119=>q<=16383;state<=s120; -- 0
WHEN s120=>q<=16383;state<=s121; -- O
WHEN s121=>q<=16383;state<=s122; -- O
WHEN s122=>q<=16383;state<=s123; -- 0
WHEN s123=>q<=16383;state<=s124; -- O
WHEN s124=>q<=16383;state<=s125; -- O
WHEN s125=>q<=16383;state<=s0; -- O
END CASE;
END IF;
END PROCESS;
END a;

--模可变计数器模块--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt IS
PORT(clk, ld:IN STD_LOGIC;
d: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
q:BUFFER STD_LOGIC_VECTOR (13 DOWNTO 0);
z:OUT STD_LOGIC);
END;
ARCHITECTURE a OF cnt IS
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk='1') THEN
IF ld='1' THEN
q<=q+1;
ELSE
q<=d;
END IF;
END IF;
END PROCESS;
PROCESS (q)
BEGIN
IF q="11111111111111" THEN
Z<='1';
ELSE
Z<='0';
END IF;
END PROCESS;
END a;
--占空比均衡控制模块--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cntrl IS
PORT(clk, c1, c0: IN STD_LOGIC;
z, en1, en0:OUT STD_LOGIC);
END;
ARCHITECTURE a OF cntrl IS
TYPE mystate IS (s0, s1);
SIGNAL state: mystate;
BEGIN
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk='1' ) THEN
CASE state IS
WHEN s0=>
IF c1='1' THEN
state<=s1;
ELSE
state<=s0;
END IF;
WHEN s1=>
IF c0='1' THEN
state<=s0;
ELSE
state<=s1;
END IF;
END CASE;
END IF;
END PROCESS;
PROCESS(state)
BEGIN
CASE state IS
WHEN s0=>
Z<='1';
en1<='1';
en0<='0';
WHEN s1=>
END CASE;
END PROCESS;
END a;